This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a CMOS logic circuit capable of securely carrying out ON/OFF control of MOS transistor for controlling current in the stand-by state even if the power supply voltage is lowered.
A conventional MT-CMOS circuit (Multi Threshold-CMOS circuit) is shown in FIG. 20.
As shown in FIG. 20, the conventional semiconductor integrated circuit device includes a CMOS logic circuit CM, and a P-channel MOS transistor MP2 for controlling current in stand-by state.
Hitherto, the MT-CMOS circuit is caused to be operative at a low voltage for the purpose of realization of low power consumption. For this reason, P-channel MOS transistor MP1 and N-channel MOS transistor MN1, etc. forming the CMOS logic circuit CM are caused to have low threshold value to suppress delay of propagation of signal at the logic gate. For example, the threshold value of the P-channel MOS transistor MP1 is caused to be -0.2 V and the threshold value of the N-channel MOS transistor MN1 is caused to be 0.2V, etc.
However, even with the circuit configuration including MOS transistors of low threshold value, there results in an increased value of leakage current also in the state where the circuit operation is halted (stand-by state). This cannot be disregarded. In view of the above, there was employed a configuration in which P-channel MOS transistor MP2 of high threshold value (e.g., -0.7 V, etc.) is inserted between the power supply line and the MOS transistors of low threshold value constituting the CMOS logic circuit. Further, the P-channel MOS transistor MP2 was turned OFF by applying the same voltage as the power supply voltage VDD to its gate in the stand-by state to thereby reduce such leakage current. On the other hand, the P-channel MOS transistor MP2 was turned ON by applying 0V to its gate in the operating state to thereby deliver power supply voltage VDD to the CMOS logic circuit (see, e.g., "1V operation MTCMOS DSP employing low voltage applicable power control mechanism" (particularly "MTCMOS circuit" of FIG. 2) by Mr. Shinichiro Mutoh et al., NTT LSI Research Institute, Technical Report of the Institute of Electronics and Communication Engineering of Japan, Vol. 96, No. 107, pp. 15-20, Technical Research Report of the Institute of the Electronic Information and Communication of Japan).
However, in the prior art, there are problems as described below. Namely, at the time of stand-by state of MT-CMOS, power supply voltage VDD is applied to the source of the P-channel MOS transistor MP2 for reducing leakage current and 0V which is low level is applied to the gate. Therefore, as the gate-source voltage VGS of the P-channel MOS transistor MP2, as far as VDD is only applied even at the maximum. Accordingly, when the P-channel MOS transistor MP2 is caused to be operative at a low voltage such that the power supply voltage and the threshold value of the transistor are close to each other, it cannot be sufficiently turned ON.
In such a case, the channel width must be enlarged in order to lower ON resistance of the P-channel MOS transistor MP2. As a result, the chip area is increased. Moreover, when the power supply voltage is caused to be less than the threshold value of the P-channel MOS transistor MP2, it becomes difficult to allow this transistor to be operative. It is the premise that transistor of high threshold value is used as the P-channel MOS transistor MP2 so that leakage current sufficiently becomes small when it is caused to be turned OFF at the time of stand-by (stand-by state) for the purpose of reducing leakage current in the stand-by state. Accordingly, when the threshold value is assumed to be -0.7 V, the minimum power supply voltage from a viewpoint of practical use is considered to be about 1V (the variable range of the threshold value is assumed to be -0.7 V.+-.0.1 V, and the change in the power supply voltage is assumed to be 1 V.+-.10%). Thus, when the power supply voltage becomes equal to, e.g., 0.5 V, the operating voltage does not exceed the threshold value. As a result, ON/OFF control cannot be carried out.
As described above, in the prior art, in the case where the power supply voltage VDD is lowered, the power supply voltage and the threshold value of the MOS transistor become close to each other. As a result, ON/OFF control becomes difficult. In addition, there results increased channel width in ON state. Ultimately, the MOS transistor becomes difficult to function.